1. Field of the Invention
The present invention relates generally to testing devices and, more particularly, to memory testing devices and methods.
2. Description of Related Art
In the era of very large scale integrated (VLSI) circuits, the trend in the fabrication of memory devices has been to construct increasingly larger memory arrays onto constant or smaller sized die (semiconductor chips). It is common for a certain percentage of the memory cells in a memory device to be faulty. To account for this, memory devices can be constructed with a core memory comprising a large number of memory cells, and a peripheral redundant memory whose memory cells can be substituted for failed memory cells from the core memory. Memory devices are tested to determine which memory cells are defective, and therefore which memory cells from the core memory need to be replaced by memory cells from the peripheral redundant memory. Unfortunately, the difficulty of testing the memory devices increases as the number of elements on a chip grows, requiring greater amounts of resources and time.
The fabrication of today's dense VLSI memory arrays dictates that a significant portion of the manufacturing process be spent testing the memory arrays. In response, tester manufacturers have created automated testing systems that simultaneously test multiple memory devices. Tests can be performed on the memory device after fabrication while still on the silicon wafer, after being packaged as a chip, or at both times.
Memory testers used on multiple memory devices typically introduce tests on the memory devices and compare outputs from the memory devices with standard or expected values. Robotic machinery can be used to places memory chips on a test board, and to initiate electrical contact between the memory devices and the external circuitry of the memory tester. A memory tester's external circuitry is typically designed in terms of modules, with each module corresponding to a terminal of the memory device. During a test, each separate module can send data, receive data, remain idle, or perform other tasks.
Tests are executed by the exchange of signals between the memory tester and the memory device or devices. To test a memory device, address signals can be generated and fed from the tester to the memory device's input address pins, and subsequently test data input signals can be fed to the memory device's input data pins. The data input signals, once applied to the memory device, are routed to respective memory segments within the memory device before an output is advanced from the memory device. This output, when compared to a standard by the memory tester, indicates whether a selected memory cell of the memory device is operating properly.
Test signals must be able to test memory devices at their maximum operational speed, and must have a failure analysis memory large enough to record the state of each memory cell of each attached memory device. Therefore the failure analysis memory is conventionally constructed to be as large as the sum of all of the memory devices being tested, and each memory cell is tested. The failure analysis memory can cost as much as 30% of the total cost of a single testing apparatus. Thus, it is desirable to be able to reduce the amount of error catch memory needed to test a plurality of memory devices.